1. Field of the Invention
The present invention relates to a fabrication method of semiconductor devices, and more particularly, to a method of fabricating a trench capacitor of a mixed mode integrated circuit.
2. Description of the Prior Art
Mixed mode integrated circuits comprise digital devices, such as an amplifier and an Analogy/Digital converter, and analog devices, such as an adder, in the logic area of the semiconductor chip. Mixed mode integrated circuits also comprise devices composed of MOS and capacitors.
It is known in the art to form a capacitor of a mixed mode integrated circuit, as shown in FIG. 1. Shallow trench isolation regions (STI) 12, the transistor gate structure 14, the lightly doped source/drain regions 16, the gate spacers 18 and the heavily doped source/drain regions 20 are formed in sequence on a semiconductor substrate 10. The deposited first polysilicon layer is used to form a transistor gate structure 14, and also used to form a lower electrode layer 22 of the capacitor. A dielectric layer 24 is deposited on the lower electrode layer 22 of the first polysilicon layer. A second polysilicon layer 26 is deposited thereon for an upper electrode layer of the capacitor. First polysilicon layer 22, the dielectric layer 24 and second polysilicon layer 26 form a PIP (poly insulator poly) capacitor structure.
The capacitance of the capacitor increases by increasing the surface area of the electrode. Due to the dielectric material with a high dielectric constant or the reduced thickness of dielectric layer, a dielectric layer with high dielectric ability is formed. However, in order to not generate a dielectric fault, the reduced thickness of the dielectric layer is limited. Therefore, the conventional method of increasing the capacitance is usually achieved by increasing the surface area of the electrode, or using a dielectric layer with a high dielectric constant.
In order to increase the surface area of the electrode, the conventional method uses a 3-dimensional structure, such as a cylindrical structure, or increases the height and uses the hemi spherical grain of polysilicon material for increasing the effective area of the lower electrode layer. However, the cylindrical shaped or the hemi spherical grain of polysilicon are difficult to apply in the process. This method causes the increase of the lower electrode layer height and has the obvious variation between the peripheral circuit and the lower electrode. This variation of topology increases the difficulty in the subsequence process.
In view of this, the present invention provides a method of fabricating a trench capacitor of a mixed mode integrated circuit in order to overcome the above-mentioned disadvantages.